Principal Engineer- Custom Layout (High-Speed Interface IP)

Overview

Principal Custom Layout Engineer to lead physical implementation for advanced high-speed analog and mixed-signal interface IPs, driving projects from floorplanning through tapeout and coordinating signoff and verification.

What you'll do

• Lead custom layout development for high-performance analog and mixed-signal IPs.
• Independently drive custom layout projects from floorplanning through tapeout.
• Own physical implementation for critical blocks including rCTLE, DFE, PLL, and related components.
• Define floorplanning strategies targeting performance, area, power, and yield goals.
• Perform transistor-level and device matching-aware layouts using best practices.
• Run physical verification and signoff including DRC, LVS, ERC, PERC, density checks, and EMIR analysis.
• Coordinate with Analog Design, Digital Design, SI, Packaging, and Product Engineering for execution and support silicon bring-up and characterization.

What you'll need

• 15+ years of custom layout experience in industry.
• 15+ years of industry experience specifically in custom layout design.
• Proven delivery of silicon-proven designs in advanced process nodes such as 5nm and 3nm.
• Extensive experience in custom layout of analog and mixed-signal circuits in advanced CMOS technologies.
• Strong understanding of analog layout fundamentals and device matching techniques.
• Strong understanding of high-speed signal routing, noise coupling mechanisms, and parasitic extraction and optimization.
• B.Tech/M.Tech in Electrical Engineering, Electronics Engineering, VLSI Design, or related discipline from a reputed university.

Details

• Location: Bengaluru, KA, India.