Memory Layout Design Engineer

Overview

Memory Layout Design Engineer responsible for end-to-end memory layout deliverables with quality and schedule, aligned to layout guidelines and new process rules.

What you'll do

• Apply layout guidelines, new process rules, and technical requirements to produce high-quality layouts.
• Manage scheduling, timelines, and layout floor-planning activities.
• Deliver start-to-end layout deliverables while meeting planned schedules.
• Adapt to new methodologies and communicate effectively with the SOC/library team.
• Plan signal and power using layout guidelines and understand RC requirements.
• Conduct physical verification activities such as LVS, DRC, ERC, Antenna, and ElectroMigration.

What you'll need

• Minimum 3 years of experience with strong layout knowledge.
• Bachelor's degree.
• Proficiency with Cadence tools including Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools.
• Experience with CALIBRE and Hercules verification tools.
• Strong layout knowledge in submicron processes including A14, 2nm, 3nm, 5nm, and 7nm.
• Experience in digital layout including Standard cell, Memory, and I/O.

Nice to have

• Analog layout experience.
• AI/automation in layout, script programming, and SKILL programming.
• Experience with memory compilers.

Details

• Work involves coordination with the SOC/library team.