Staff Engineer, IP Dev Layout

Overview

Staff Engineer focused on analog/mixed-signal custom digital block design and full chip-level integration support for IP development.

What you'll do

• Design and develop critical analog, mixed-signal, custom digital blocks, and full chip level integration support.
• Perform layout verification including LVS, DRC, and Antenna checks.
• Carry out quality checks and support documentation for layout projects.
• Deliver block-level layouts on time with acceptable quality.
• Lead planning with area/time estimation, scheduling, and execution to meet project schedules.
• Coordinate with global engineering teams to support successful layout project delivery.

What you'll need

• 8 to 15 years of experience in analog/custom layout build in advanced CMOS process.
• Hands-on experience in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS.
• Experience creating layouts for critical blocks including temperature sensor, PLL, ADC, DAC, LDO, bandgap, and others.
• Good understanding of analog layout fundamentals such as matching, electro-migration, and latch-up.
• Ability to understand build constraints and implement high-quality layouts.
• Excellent problem-solving skills in physical verification of custom layout.
• BE or MTech in Electronic/VLSI Engineering.

Details

• Location: Hyderabad, Telangana, India.