Principal Engineer- HIG HBM Layout

Overview

Principal Engineer responsible for end-to-end HBM layout execution for analog, mixed-signal custom blocks and full-chip integration.

What you'll do

• Lead end-to-end analog, mixed-signal, custom digital block layout and full-chip integration for HBM products.
• Own full-chip technical decisions across analog, digital, memory, ESD, and EM/IR to optimize PPA.
• Drive project planning and execution including estimation, scheduling, task delegation, and milestone tracking.
• Oversee layout verification activities such as LVS, DRC, and antenna checks with closure documentation.
• Lead and mentor the layout team through design reviews and junior execution guidance.
• Collaborate with global cross-functional teams across Design, Verification, IP, and Packaging.

What you'll need

• 15+ years analog/custom layout experience in advanced CMOS processes.
• 4+ years developing teams and project experience.
• Experience leading multiple projects and tape-outs.
• Cadence VLE/VXL and Calibre DRC/LVS expertise required.
• Strong layout and floorplanning skills plus manual routing.
• Excellent verbal and written communication skills.

Details

• Location: Hyderabad - Phoenix Aquila, India.