Senior Staff Engineer

Overview

Physical Design Engineer role focused on physical implementation and timing closure of complex, low-power SoCs for IoT and MCU markets.

What you'll do

• Drive physical design and timing closure for hierarchical blocks and full-chip SoC designs.
• Execute physical design flow stages including floorplanning, I/O planning, and package co-design.
• Perform power grid design, placement and routing, and clock tree synthesis (CTS).
• Run timing optimization and closure and conduct static and dynamic IR drop analysis.
• Complete physical verification and signoff checks.
• Implement and optimize low-power design methodologies such as multiple voltage domains and power islands.
• Develop and improve physical design methodologies and automation flows to raise QoR and productivity.

What you'll need

• Hands-on end-to-end SoC physical design and timing closure experience.
• Deep understanding of low-power implementation techniques including multiple voltage and power domains.
• Knowledge of I/O planning and package co-design considerations.
• Experience using industry-standard EDA tools for physical design, verification, and signoff.
• Scripting/automation skills using Shell, Perl, Tcl, and Make-based flows.
• Knowledge of advanced semiconductor technology nodes (40nm, 28nm, 22nm).
• Bachelor’s or Master’s degree in Electronics Engineering, Microelectronics, VLSI Design, or related field.

Details

• Location: Bangalore BTP.