Overview
Principal Engineer, Static Timing Analysis (STA) responsible for full-chip timing closure and signoff for complex AI connectivity silicon.
What you'll do
- Own end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC).
- Drive timing convergence on advanced process nodes from early floorplan through tapeout.
- Analyze and resolve setup, hold, recovery/removal, and CDC timing violations at the chip level.
- Define and evolve STA methodology, constraints (SDC) strategy, and signoff criteria.
- Develop and automate STA flows using PrimeTime, PrimeTime SI, and related signoff tools.
- Partner with Physical Design, RTL, DFT, CAD, and Package teams and ensure consistent timing handoffs.
- Mentor STA engineers and review timing reports, ECOs, and signoff collateral.
What you'll need
- Have a Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
- Have 10+ years of hands-on experience in Static Timing Analysis on complex ASIC/SoC designs.
- Have a proven track record of full-chip top-level STA signoff on at least one tapeout at advanced nodes (7nm or below).
- Have deep expertise with PrimeTime, PrimeTime SI, and SDC constraint development.
- Have strong understanding of clocking architectures and CDC, including OCV/AOCV/POCV and crosstalk/IR-aware timing.
- Be proficient in scripting (Tcl, Python, Perl) for STA flow automation and report analysis.
Details
- Location: Bengaluru, Karnataka, India.
Read the full description and apply on the company’s own careers page.
