Senior Digital Design Engineer

Overview

Senior Digital Design Engineer focused on synthesis and front-end implementation for digital ASIC/SoC design, turning RTL into optimized gate-level netlists while meeting performance, power, and area targets.

What you'll do

• Perform synthesis of RTL designs for digital blocks and sub-systems.
• Develop and implement timing constraints (SDC) to reach target frequencies.
• Run STA to identify critical paths and support timing closure.
• Execute formal verification (LEC) to ensure RTL and netlist functional equivalency.
• Analyze and optimize power consumption at the front-end stage.
• Estimate and optimize area to meet chip size requirements.
• Build automation scripts (Tcl/Python/Perl) for synthesis flows and analysis.

What you'll need

• 5+ years of relevant experience in digital ASIC/SoC design with synthesis and front-end implementation.
• Bachelor’s or Master’s degree in Electrical Engineering/Computer Engineering or related field.
• Proficiency with industry-standard synthesis tools such as Synopsys Design Compiler or Fusion Compiler (or similar).
• Strong STA knowledge and experience with tools such as Synopsys PrimeTime.
• Experience using formal verification tools such as Synopsys Formality or Cadence Conformal (LEC).
• Knowledge of upf and low-power design techniques plus power analysis concepts.
• Solid Verilog/SystemVerilog skills and familiarity with Tcl/Python/Perl scripting.

Details

• Location: Pune.