Principal Engineer - STA/Synthesis

Overview

As a Principal Verification STA Engineer, you will design and analyze digital and analog circuits for memory product development and drive static timing analysis activities.

What you'll do

• Perform static timing analysis (DRAM block-wise and top-level analysis) and cell-level analysis.
• Write constraints and analyze STA reports.
• Understand circuits block-wise and identify/report timing violations to the design team.
• Own timing closure for core die STA.
• Perform parasitic modeling and assist in design validation, reticle experiments, and tape-out revisions.
• Execute verification processes using modeling and simulation with industry standard simulators.
• Contribute to cross-group communication toward standardization.

What you'll need

• Minimum of 10+ years of experience required.
• Experience with static timing analysis.
• Experience writing constraints.
• Experience with parasitic modeling.
• Experience using modeling and simulation with industry standard simulators.
• Ability to characterize basic STD cells.

Details

• Location: Hyderabad, Telangana, India.