Principal Engineer - STA/Synthesis

Overview

Principal Verification STA Engineer responsible for designing and analyzing digital and analog circuits for memory product development.

What you'll do

• Design and analyze digital and analog circuits used in developing memory products.
• Write constraints and perform timing closure for core die STA.
• Run static timing analysis for DRAM blocks, including top-level and cell-level analysis.
• Analyze STA reports, report violations to the design team, and own closure.
• Perform parasitic modeling and assist in design validation, reticle experiments, and tape-out revisions.
• Use modeling and simulation with industry-standard simulators for verification processes.

What you'll need

• Minimum of 10+ years of experience.
• Experience with static timing analysis across DRAM block-wise, top-level, and cell-level.
• Ability to write constraints and support timing closure for core die STA.
• Circuit understanding block-wise and full-chip level reporting.
• Experience with parasitic modeling and design validation support.
• Experience performing verification with modeling and simulation using industry standard simulators.

Details

• Location: Hyderabad - Phoenix Aquila, India.