RTL Synthesis Methodology Principal/ Sr Staff Engineer

Overview

Principal/Senior Staff Engineer to lead the definition and deployment of next-generation RTL-to-Gate synthesis methodology for Qualcomm's SoCs, optimizing Power, Performance, and Area (PPA) and driving signoff closure for Synthesis, Low Power, STA, and LEC.

What you'll do

• Lead the definition, development, and deployment of the global RTL Synthesis Reference Flow (Fusion Compiler, Genus) across multiple technology nodes (5nm, 3nm, 2nm and beyond).
• Drive RTL2GDS co-optimization initiatives, collaborating with RTL and PD teams to deliver measurable PPA improvements through advanced synthesis techniques.
• Architect and maintain the Low Power (UPF/IEEE 1801) implementation methodology, and drive the flow for Static Low Power checking (CLP/VCLP) and power intent verification from RTL to Netlist.
• Own Logic Equivalence Checking (LEC) flows (Conformal/Formality) for complex data paths, retiming, and functional ECOs.
• Drive constraints management and early STA signoff quality (Fishtail, PrimeTime).
• Act as the primary technical interface with EDA vendors (Synopsys, Cadence), drive tool roadmaps, manage beta evaluations, and file critical enhancements to close gaps between foundry claims and actual product PPA.
• Oversee development of scalable, robust automation (Python/Tcl) to integrate synthesis with DFT insertion and Netlist Signoff.
• Mentor a team of CAD engineers, providing technical guidance on complex debugs, flow architecture, and best practices.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience, OR Master's degree in a related field and 7+ years of Hardware Engineering or related work experience, OR PhD in a related field and 6+ years of Hardware Engineering or related work experience.
• 15+ years of solid experience in ASIC CAD flow development, Physical Design, or Synthesis Methodology.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Deep expertise in industry-standard Synthesis tools (Synopsys Fusion Compiler (FC)/Design Compiler (DC-NXT) and Cadence Genus).
• Proven track record of solving complex PPA challenges.
• Hands-on mastery of Logic Equivalence Checking (LEC) tools (Cadence Conformal LEC, Synopsys Formality), including debug of difficult non-equivalent points in datapath-heavy designs.
• Strong understanding of Static Timing Analysis (STA), SDC constraints generation, and validation (PrimeTime, GCA/Fishtail).
• Advanced proficiency in Tcl and Python for flow development and data analysis.

Nice to have

• Deep knowledge of UPF/CPF flows, multi-voltage domains, power gating, retention.
• Experience with Physical Synthesis technologies (Def-based flow, iSpatial, Physical guidance) and correlation with P&R tools (Innovus/ICC2).
• Familiarity with RTL-integrated DFT flows (Scan stitching, MBIST insertion) and their impact on timing/congestion.
• Demonstrated ability to lead cross-site projects, influence design methodologies, and manage stakeholder expectations in a fast-paced environment.
• Experience with AI/ML-driven CAD tools (e.g., Fusion.ai, Cerebrus) for design space exploration.

Details

• Location: Bangalore, India.
• Job area: Engineering Group > Hardware Engineering.