Senior Engineer, CAD Layout

Overview

Senior CAD Engineer responsible for improving EDA tools and automation workflows supporting physical layout, verification, and CMOS integrated-circuit design.

What you'll do

• Support memory layout teams by solving daily challenges and developing lasting solutions.
• Identify improvement areas and develop innovative automation solutions.
• Lead AI-assisted layout flow implementation for placement, routing, and optimization.
• Evaluate and implement tools to improve layout development flows.
• Develop methodologies for reliable layouts and faster time to market.
• Mentor junior team members.
• Deploy AI-enabled methods for semi-automated floorplanning and parasitic estimation.

What you'll need

• 5+ years of experience in layout automation, physical verification, or related domains.
• Experience customizing design environments and automation utilities for memory layout productivity.
• Experience with custom-memory place-and-route flows and tools such as Cadence Virtuoso or Synopsys Custom Compiler.
• Working knowledge of Linux.
• Programming exposure to Skill, Perl, Python, or Tcl.
• Understanding of CMOS manufacturing, layout rules, EMIR, RC extraction, ESD, and latch-up.
• Bachelor's or master's degree in Electronics, Electrical, or Computer Engineering.

Nice to have

• Experience with Totem, VoltusXFA, or XA PDN analysis tools.
• Experience debugging DRC, ERC, LVS, DFM, antenna, and Calibre/ICV rule-deck issues.

Details

• Location: Hyderabad, India.