Senior Engineer I - Verification

Overview

Senior Verification Engineer for secure computing product work in the SCG group, supporting digital logic design efforts for embedded controller hardware.

What you'll do

• Own verification of complex blocks and subsystems within ARM-based SoCs.
• Run block-level and chip-level functional verification.
• Define test plans from design specifications and implement constrained-random and directed tests.
• Develop test environments using SystemVerilog and UVM verification methodologies.
• Integrate with RTL and support basic simulation bring-up.
• Generate coverage, analyze results, correlate with the test plan, and drive coverage closure.

What you'll need

• 4–6 years of experience in ASIC/SoC functional verification.
• Bachelor’s/Master's in Electrical/Electronic Engineering or related field.
• Strong expertise in SystemVerilog and UVM methodology.
• Hands-on experience developing block/subsystem/SoC-level verification environments.
• Solid understanding of AMBA, USB, I2C, SPI, and eSPI protocols.
• Familiarity with scripting (Python/TCL/Perl) for automation.
• Good programming skills using C and C++.

Details

• Location: Chennai, India.
• Travel time: 0% - 25%.