Senior Layout Engineer – DPG Layout

Overview

Senior Layout Engineer for DPG Layout at Micron Technology, owning the development and physical implementation of critical analog, mixed-signal, and custom digital blocks, and leading layout work with AI-assisted and automated workflows.

What you'll do

• Own the development and physical implementation of critical analog, mixed-signal, and custom digital blocks, including block-level and full-chip layout ownership.
• Lead layout implementation using AI-assisted and automated workflows, applying copilot-based assistants, agentic AI flows, and rule-aware automation to accelerate placement, routing and optimization.
• Perform and automate layout verification activities, including DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR and quality checks.
• Drive on-time delivery of blocks and partition-level layouts with predictable quality and risk prediction/mitigation plans.
• Develop and deploy AI-enabled methodologies for semi-automated floorplanning, parasitic estimation, layout consistency checks and best-practice enforcement, and repetitive layout task elimination via SKILL, Python, TCL or agent-based flows.
• Demonstrate technical leadership in planning, area and cycle-time estimation, delegation and execution.
• Guide and mentor engineers in analog layout fundamentals, automation-first approach, design-for-quality and design-for-yield practices.
• Collaborate closely with Design, CAD, Verification, Reliability, and Program Management teams, clearly communicating technical risks, schedule impacts and any optimization opportunities.
• Drive continuous improvement by identifying manual bottlenecks and converting them into scalable automated flows.

What you'll need

• 6+ years of experience in analog/custom layout design in advanced CMOS technology nodes.
• Strong expertise in Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, with hands-on ownership of verification closure.
• Proven experience in layout of critical analog blocks, including but not limited to temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps, etc.
• Hands-on experience with memory layouts, including DRAM, SRAM, CAM, OTP and understanding of array-to-periphery integration.
• Deep understanding of analog layout fundamentals, including matching and symmetry, EM, latch-up, coupling, crosstalk, IR-drop, shielding, guard-ring strategies, parasitic effects.
• Strong ability to interpret design intent and constraints and translate them into high-quality, manufacturable layouts.
• Proven expertise in defining, developing, and scaling AI-driven automation and AI-assisted methodologies for complex layout workflows.
• Demonstrated problem-solving skills in physical verification, debug, and layout optimization dedicated to improving yield.
• B.Tech in Electronics, Electronics & Communication, or VLSI Engineering, or M.Tech in VLSI Design, Microelectronics, or Electronics Engineering.

Details

• Location: Hyderabad, Telangana, India.