Senior Principal Engineer

Overview

Work as a Digital Design Engineer focused on scan insertion, ATPG and GLS. The role involves understanding DFT architecture and enabling scan insertion flows during synthesis.

What you'll do

• Understand the DFT architecture of the design.
• Provide scan insertion collaterals to the implementation team to enable scan insertion flows during synthesis.
• Contribute to ATPG at partition and SoC level.
• Work with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis.
• Collaborate across functions.

What you'll need

• Hands-on experience in scan insertion, ATPG and GLS.
• Proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler and Cadence Encounter Test.
• Experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis.
• Familiarity with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG).
• Effective communication and teamwork skills.

Details

• Location: Noida.