Senior Principal Engineer - Verification / AMS / SerDes

Overview

Senior Principal Engineer will lead verification strategy and execution for complex high-speed SerDes and AMS/mixed-signal IPs across multiple process nodes.

What you'll do

• Own end-to-end verification strategy and execution for complex SerDes/AMS/mixed-signal IPs across nodes.
• Define and drive verification architecture across digital, AMS, firmware-assisted, and system-level verification.
• Lead design-verification convergence, including register definition, calibration flows, and feature feasibility.
• Resolve complex cross-domain issues across RTL, AMS, firmware, VIPs, and silicon behaviors.
• Act as technical authority for hard verification, coverage, debug, and sign-off challenges.
• Lead GLS strategy, power-aware verification, CDC/RDC validation, and post-silicon correlation.
• Mentor engineers and drive methodology/tooling automation and productivity improvements.

What you'll need

• 17+ years of strong hands-on experience in verification of IP/AMS systems.
• Deep expertise in high-speed SerDes verification areas (e.g., PCIe, Ethernet, D2D, PAM4/PAM2).
• Deep expertise in AMS/mixed-signal verification.
• Strong proficiency in SystemVerilog and UVM and advanced verification methodologies.
• Experience integrating protocols/VIPs using tools such as Synopsys, Cadence, Mentor, or Avery.
• Hands-on experience with GLS, power-aware verification, timing-aware flows, and silicon bring-up support.
• Ability to analyze and debug issues from pre-silicon through post-silicon correlation.