Serdes PHY Analog Design Engineer

Overview

Serdes PHY Analog Design Engineer on the BDC SerDes Mixed-Signal design team, delivering next-generation custom high-speed SerDes PHY designs for SoCs.

What you'll do

• Design multiple analog building blocks, including LDO, high-speed TX and RX (equalizer, sampler, PI, deserializer), bias and reference circuits.
• Design analog and/or digital PLLs for frequency synthesis and/or SerDes applications, including charge pump, loop filter, VCO/DCO, PFD/TDC and high-speed dividers.
• Model PLL loop dynamics and jitter sources (RJ and DJ).
• Take a design through schematic to post-layout verification, integration sign-off and post-silicon bring-up.
• Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience, or Master's degree in a related field and 3+ years of Hardware Engineering or related work experience, or PhD in a related field and 2+ years of Hardware Engineering or related work experience.
• 8+ years of experience as an analog circuit designer.
• Hands-on experience in analog circuit design.
• Understanding of advanced FinFET process effects on designs and layout.
• Experience using SPICE simulators, ADEXL and Virtuoso.
• Experience with post-silicon bring-up and debug.
• Shell/Perl/Python scripting to automate circuit design and verification work.
• Ability to work with teams across the globe, with good communication and presentation skills.
• For lead position: performed PHY lead roles, including PHY integration to SoC and interaction with post-silicon teams such as HSIO, ATE, SVE and CE.

Nice to have

• Good understanding of peripheral PHY protocols (USB, UFS, PCIe).
• Mixed-signal design experience.

Details

• Location: Bangalore, India.