Staff Engineer, ASIC Analog Design

Overview

Staff-level analog/mixed-signal design role on Micron's high-speed PHY team, owning analog sub-blocks in advanced technology nodes (12nm and below).

What you'll do

• Own analog sub-blocks within the PHY and drive specification, design, simulation, reliability, and mixed-mode verification.
• Leverage AI-enabled tools to improve productivity and decision-making.
• Drive layout implementation through mask designers while ensuring compliance with process rules and DFM requirements.
• Participate in design reviews with internal teams and customers, explaining design choices and robustness.
• Collaborate with cross-functional teams across multiple global locations.
• Create IP EDA views including behavioral models, Verilog-A, timing views, and abstracts.
• Participate in silicon bring-up, characterization, and correlation of silicon results with models and simulations.
• Mentor and guide junior engineers.

What you'll need

• M.S./M.Tech or B.S./B.E. in Electronics.
• 5+ years of experience.
• Strong analog/mixed-signal CMOS circuit design experience in deep sub-micron technologies (2nm to 28nm).
• Experience in high-speed memory interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes interfaces (PCIe, MIPI, HDMI, USB, SATA, etc.).
• Full ownership experience of at least one critical PHY sub-block such as PLL, DLL, CDR, high-speed receiver with equalization, transmitter front-end, or high-speed data path.
• Deep understanding of analog and mixed-signal design concepts with high-speed link experience.
• Mandatory experience in SerDes and/or parallel interfaces.
• Mandatory experience with TX/RX equalization techniques (FFE, CTLE, DFE).
• Experience with CDR and clocking architectures.
• Hands-on experience in FinFET technologies (10nm and below).
• Ability to develop block-level specifications based on link budgets.
• Experience in system-level modeling using Verilog-A and/or Python.
• Experience working with packaging and board teams.
• Knowledge of ESD design considerations.
• Experience in lab testing and collaborating with validation teams for data analysis.
• Experience designing high-speed I/O cells such as DDR, LVDS, HSTL, and CML.
• Experience with power delivery circuits including bandgap, LDO, and bias circuits.
• Strong understanding of AMS design, advanced CMOS, and FinFET technologies.
• Knowledge of mismatch analysis, Monte Carlo simulations, transistor-level noise analysis, and deep sub-micron device physics.
• Experience supervising complex analog layouts and defining IP floorplans.
• Hands-on experience with industry-standard tools such as Cadence ADE, Spectre, AMS verification, EM/IR flows, MATLAB, and Calibre.
• Working knowledge of mixed-mode simulation, signal integrity, and ESD analysis.

Details

• Location: Bengaluru, Karnataka, India.