Staff Engineer - ESD Design

Overview

Lead ESD architecture, circuit design, modeling, signoff, silicon debug, reliability, qualification, physical design, and technology engagement for high-speed I/O portfolios and sophisticated SoCs. Serve as the ESD subject-matter guide across the organization while driving reusable ESD IP, methodologies, and design standards.

What you'll do

• Define and own ESD architecture and protection strategy for high-speed I/O portfolios including HBM, DDR, LPDDR PHY I/Os, PCIe, USB, Ethernet, MIPI, and proprietary interfaces.
• Lead ESD–I/O co-design trade-off decisions balancing aggressive ESD targets, ultra-low capacitance and leakage requirements, eye margin, jitter, bandwidth, return loss, and impedance matching.
• Drive architectural choices for snapback clamps, rail clamps, diode steering networks, triggered and advanced ESD devices, and domain isolation and sequencing protection for sophisticated SoCs.
• Perform and guide ESD circuit design and analysis at block and full-chip level.
• Establish simulation methodologies for transient ESD stress, dynamic clamp triggering and current handling, and I/O performance impact including capacitance loading, ringing, and overshoot/undershoot.
• Own ESD modeling correlation with device and modeling teams on compact models covering dynamic resistance, triggering, and CV behavior.
• Drive correlation between SPICE simulations, TLP/VF-TLP, and silicon results.
• Act as the final technical authority for ESD design reviews and signoff.
• Lead silicon-level ESD failure analysis across products and generations.
• Drive root cause analysis for HBM/CDM failures, leakage and performance degradation, and latch-up and substrate-coupling issues.
• Collaborate with reliability to define corrective actions and preventive methodologies.
• Own ESD qualification strategies and ensure first-pass silicon success.
• Define company-wide layout guidelines for ESD devices, including current uniformity, ballasting, guard rings, substrate/well engineering, isolation standard processes, power clamp placement, and return path integrity.
• Partner with technology, process, and PDK teams to influence ESD-friendly process features, enable scalable ESD solutions in sophisticated nodes, and ensure ESD robustness across multiple packages and I/O ring configurations.
• Serve as the ESD subject-matter guide across the organization.
• Provide strategic guidance to I/O and PHY design teams, PDN, package and board-level engineers, and product engineering and manufacturing.
• Mentor and technically develop junior and senior ESD/design engineers.
• Drive methodology reuse, IP standardization, and design standard processes across programs.
• Leverage AI-assisted coding techniques and AI tools to improve efficiency and automate design, analysis, tools, and workflows.

What you'll need

• B.Tech, M.Tech, or PhD in Electrical/Electronic Engineering or a related field.
• 8+ years of hands-on experience in ESD circuit design and protection architecture.
• 8+ years of hands-on experience in high-speed I/O or mixed-signal chip environments.
• Consistent track record of delivering production silicon meeting aggressive ESD and performance targets.
• Consistent track record of leading ESD technical decisions for sophisticated, high-volume products.
• Deep expertise in HBM, CDM, MM, and latch-up mechanisms.
• Deep expertise in high-speed signal integrity fundamentals and constraints.
• Strong command of SPICE-based simulators, including Spectre and HSPICE.
• Strong command of physical layout review and ESD signoff flows.
• Recognized technical authority with strong executive-level interpersonal skills.
• Ability to make and defend data-driven architectural trade-offs.
• Mentor-first attitude with passion for growing technical talent.
• Comfort operating in ambiguous, fast-paced, first-principles problem spaces.
• Proven ability to leverage AI-assisted coding techniques to improve efficiency or automate design and analysis methodologies.

Details

• Location: Bengaluru, India.