Staff Engineer, IP Dev Layout

Overview

Staff Engineer for IP Dev Layout, focused on designing and developing critical analog, mixed-signal, and digital blocks and supporting full chip level integration layouts.

What you'll do

• Design and develop critical analog, mixed-signal, custom digital blocks, and support full chip level integration.
• Perform layout verification including LVS, DRC, and Antenna checks.
• Carry out layout quality checks and support documentation.
• Ensure on-time delivery of block-level layouts with acceptable quality.
• Lead planning, area/time estimation, scheduling, and execution to meet project timelines.
• Coordinate effectively with global engineering teams to support layout project success.

What you'll need

• Experience of 8 to 15 years in analog/custom layout build in advanced CMOS processes across multiple technology nodes.
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is required.
• Hands-on experience creating layouts for critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, and Ref Generators.
• Good understanding of analog layout fundamentals including matching and electro-migration.
• Ability to understand layout effects on speed, capacitance, power, and area.
• Skills in physical verification of custom layout with excellent problem-solving.
• Excellent verbal and written communication skills.
• Proactive use of AI-related tools in day-to-day tasks is expected.
• Education: BE or MTech in Electronic/VLSI Engineering.

Details

• Location: Hyderabad - Phoenix Aquila, India.