Verification Engineer, PCIE

Overview

Verify the design and implementation of next-generation PCI Express controllers for GPUs and SOCs as a Senior Verification Engineer.

What you'll do

• Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Understand the design specification and implementation.
• Define the verification scope.
• Develop test plans, tests, and the verification infrastructure.
• Verify the correctness of the design.
• Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

What you'll need

• B.Tech./ M.Tech or equivalent experience.
• 1+ years of relevant experience.
• Experience in verification at Unit/Sub-system/SOC level.
• Expertise in Verilog and SystemVerilog.
• Experience in comprehensive verification of IP or interconnect protocols such as PCI Express, USB, SATA.
• Experience in developing and working in functional coverage based constrained random verification environments.
• Background in DV methodologies like UVM/VMM.
• Exposure to industry standard verification tools for simulation and debug.

Nice to have

• Excellent knowledge of PCIE protocol - Gen3 and above.
• Good understanding of the system level architecture of PCIE/CXL-based designs.
• Perl, Python or similar scripting and SW programming language experience.
• Good debugging and analytical skills.
• Good interpersonal skills.
• Dream to work as a great teammate.

Details

• Location: Bengaluru, India.