Jobs By Abekus

Vhdl Questions Set 6:

Quiz Mode

The VHDL code above describes a:

2:1 Multiplexer

2:1 Encoder

1:2 Demultiplexer

None of the above

Solution:

What is the decimal equivalent of x in the following code?
SIGNAL x : OUT SIGNED (3 DOWNTO 0 ); x <= “1101”;

-5

-3

-14

Solution:

In the p-well method, the parasite capacitance is __________ compared to the n-well method.

lower

higher

the same

negligible

Solution:

If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is?

x <= a.b

x <= a OR b

x <= a + b

x <= a && b

Solution:

In an assignment statement, OUT signal can be used only to the ___________

Left of >= operator

Left of <= operator

Right of <= operator

Right of >= operator

Solution:

How to define a WAIT UNTIL statement?

WAIT UNTIL boolean_condition_or_expression;

WAIT UNTIL signal_name;

WAIT UNTIL time_value_or_expression;

WAIT UNTIL boolean_expression time_value;

Solution:

What does VHDL stand for?

Very High-Speed Integrated Circuits Hardware Description Language

Very Highly Sensitive Integrated Circuits

Very High Speed Internet for Circuits

Very Highly Sensitive Internet for Circuits

Solution:

What is the meaning of component instantiation in digital design?

To remove any component from the design

To use the component in the circuit

To describe the external interface of the component

To declare the gate-level components

Solution:

What is true for a concurrent assignment statement?

The statement is executed once

The statement is executed twice

The statement is executed as many times as the value changes

The value of the left operand is assigned to the right operand

Solution:

Which of the following is true about Generics?

Generics can be assigned information as part of a simulation run

Generics cannot be assigned information as part of a simulation run

Generics pass data to an entity which is not instance-specific

Results of a simulation can modify the value of generics

Vhdl Questions Set 6:

The VHDL code above describes a:

Solution:

What is the decimal equivalent of x in the following code?
SIGNAL x : OUT SIGNED (3 DOWNTO 0 ); x <= “1101”;

Solution:

In the p-well method, the parasite capacitance is __________ compared to the n-well method.

Solution:

If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is?

Solution:

In an assignment statement, OUT signal can be used only to the ___________

Solution:

How to define a WAIT UNTIL statement?

Solution:

What does VHDL stand for?

Solution:

What is the meaning of component instantiation in digital design?

Solution:

What is true for a concurrent assignment statement?

Solution:

Which of the following is true about Generics?

Solution:

Related Question Sets:

Related Topics:

Vhdl Questions Set 6:

The VHDL code above describes a:

Solution:

What is the decimal equivalent of x in the following code?SIGNAL x : OUT SIGNED (3 DOWNTO 0 ); x <= “1101”;

Solution:

In the p-well method, the parasite capacitance is __________ compared to the n-well method.

Solution:

If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is?

Solution:

In an assignment statement, OUT signal can be used only to the ___________

Solution:

How to define a WAIT UNTIL statement?

Solution:

What does VHDL stand for?

Solution:

What is the meaning of component instantiation in digital design?

Solution:

What is true for a concurrent assignment statement?

Solution:

Which of the following is true about Generics?

Solution:

Related Question Sets:

Related Topics:

What is the decimal equivalent of x in the following code?
SIGNAL x : OUT SIGNED (3 DOWNTO 0 ); x <= “1101”;