Chassis IP Senior Design Engineer

Overview

Senior Design Engineer for Intel’s Chassis Group, delivering chassis logic/IP for SoCs within Intel.

What you'll do

• Develop logic designs using RTL coding and simulations for IP blocks and subsystems.
• Define and implement architecture/microarchitecture for an interconnect IP block and subsystem features.
• Perform quality checks and RTL optimization to improve power, performance, area, and timing.
• Evaluate design trade-offs across area, bandwidth, timing, and reliability.
• Support SoC customers with IP integration and verification workflows.

What you'll need

• Minimum 7 years of experience in logic design and RTL development.
• Proficiency in Verilog and SystemVerilog.
• Strong digital design knowledge including timing analysis and power optimization.
• Experience with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics.
• Develop/register logic designs and simulations for functional units and IP.

Details

• Primary location: India, Bangalore.
• Shift 1 (India).
• Hybrid work model: split time between on-site at the assigned site and off-site.