CPU Design Verification Assoc Engineer

Overview

CPU Design Verification Associate Engineer role focused on verifying high-performance, low-power CPU power management features in Bangalore.

What you'll do

• Verify power management functions including boot, reset, clock gating, and power gating.
• Build test plans with CPU design and verification teams.
• Execute test plans using simulation and formal verification.
• Develop checkers, assertions, and stimulus.
• Verify power intent using methodologies such as UPF.
• Validate system use cases with system architects, software teams, and SoC teams.
• Debug and triage failures across simulation, emulation, and silicon.

What you'll need

• Bachelor’s in relevant fields with 4+ years hardware engineering experience, or equivalent graduate/PhD experience per listing.
• Experience in power management verification.
• Ability to implement assembly and C-language embedded firmware.
• Experience with C/C++, scripting languages, Verilog/SystemVerilog.
• Strong understanding of CPU power management features for CPUs and CPU-based SoCs.
• Experience verifying clock gating, power gating, UPF, DVFS/DCVS, reliability, and throttling.

Details

• Location: Bangalore, India.