Director, Physical Design

Overview

Director-level Physical Design role within the ASICS Engineering Group at Qualcomm, owning physical design implementation for complex SoC/IP blocks.

What you'll do

• Own end-to-end physical design implementation from Netlist to GDSII for complex SoC/IP blocks.
• Drive Floorplanning, Power Planning (PDN), Placement, CTS, Routing, STA, and Timing Closure.
• Perform physical verification including DRC, LVS, and signoff checks.
• Collaborate with RTL, STA, DFT, Verification, and CAD teams to achieve design and tapeout goals.
• Debug and resolve timing, congestion, IR drop, and physical design challenges.
• Support successful chip tapeouts on advanced technology nodes.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• 3-6 years of hands-on experience in SoC/ASIC Physical Design.
• Strong expertise in Floorplanning, PDN, Placement, CTS, Routing, and Timing Closure.
• Experience with industry-standard EDA tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, and Calibre.
• Good understanding of physical verification, power integrity, and signoff methodologies.
• Strong debugging, problem-solving, and communication skills.

Nice to have

• Experience working on advanced nodes (16nm and below).
• Experience in high-performance CPU, GPU, AI, Mobile, Networking, or Multimedia SoCs.
• Candidates from leading semiconductor product companies are strongly preferred.

Details

• Location: Bangalore, India.