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GPU Physical Design Engineer (Senior/Lead)

Qualcomm
NewPosted today

LOCATION

Bangalore · Onsite

EXPERIENCE

3+ Years

SKILLS REQUIRED

Place and routeTiming ClosureStatic Timing AnalysisPhysical VerificationClock Tree Synthesis

Job description

Overview

Drive implementation and physical signoff of next-generation high-performance GPU designs, collaborating closely with RTL, STA, DFT, Power and SoC teams to achieve aggressive PPA targets and successful tapeouts.

What you'll do

  • Carry out physical implementation of high-performance GPU cores, including floor-planning, place and route, CTS, formal verification, physical verification (DRC/LVS), PDN, timing closure and power optimization.
  • Make PPA trade-off decisions for PPA-critical cores.
  • Drive timing convergence of high-frequency, data-path-intensive cores using advanced STA concepts.
  • Run block-level PnR convergence with Synopsys ICC2 / Cadence Innovus and timing convergence in PrimeTime SI / Tempus in the latest technology nodes.
  • Work in close collaboration with design, DFT and PNR teams to resolve constraints validation, verification, STA and physical design issues.
  • Handle technical deliverables with a small team of engineers and work towards project milestones and deadlines.

What you'll need

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering or related field and 4+ years of Hardware Engineering or related work experience, OR Master's degree in a related field and 3+ years of Hardware Engineering or related work experience, OR PhD in a related field and 2+ years of Hardware Engineering or related work experience.
  • Bachelor's/Master's degree in Electrical/Electronic Engineering from a reputed institution.
  • 3+ years of experience in Physical Design/Implementation.
  • Good exposure to PD implementation of PPA-critical cores and making right PPA trade-off decisions.
  • Strong expertise in timing convergence of high-frequency data-path-intensive cores and advanced STA concepts.
  • Well versed with block-level PnR convergence with Synopsys ICC2 / Cadence Innovus and timing convergence in PTSI / Tempus in latest technology nodes.
  • Good understanding of clocking architecture.
  • Well versed with Tcl/Perl scripting.
  • Experience working as part of a larger team and towards project milestones and deadlines.
  • Strong problem-solving skills and good communication skills.

Details

  • Location: Bangalore, India.
  • Job area: Engineering Group > Hardware Engineering.

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GPU Physical Design Engineer (Senior/Lead)