High Performance DSP core Implementation(Synthesis) Senior Engineer

Overview

Senior Engineer for High Performance DSP core Implementation (Synthesis) in the ASIC engineering area. Responsible for defining, optimizing, verifying/validating, implementing, and documenting IP/block/SoC development focused on high performance, high quality, and low power products.

What you'll do

• Apply physical synthesis and synthesis methodologies using industry-standard tools.
• Write timing constraints for synthesis and perform STA for timing closure.
• Execute timing closure and pipelining across different levels and multi-clock domain designs.
• Optimize low-power design implementation using UPF and power optimization flows (e.g., clock gating).
• Use scripting (Perl/Python and TCL) to support synthesis-related tasks and validation.
• Deliver netlist and validate timing constraints with design, DFT, and PD teams.
• Handle ECOs and perform formal verification while maintaining quality metrics.

What you'll need

• Experience range: 3+ years hands-on in synthesis and LEC.
• Knowledge of physical synthesis and synthesis methodologies.
• Experience writing timing constraints, running STA, and achieving timing closure.
• Familiarity with MCMM synthesis and optimization.
• Understanding of low-power implementation using UPF.
• Scripting skills using Perl/Python and TCL.
• Tool proficiency: Familiar with Fusion Compiler/Genus; fair knowledge of LEC and LP signoff tools.

Details

• Location: Noida, Uttar Pradesh, India.