High Performance DSP core Implementation(Synthesis) Senior Lead Engineer

Overview

Senior Lead Engineer for High Performance DSP core implementation focused on ASIC synthesis. You will implement and validate timing, optimization, and low-power synthesis flows using industry-standard EDA tools.

What you'll do

• Define, model, design, optimize, verify, validate, implement, and document IP for block/SoC development.
• Perform physical synthesis and apply synthesis methodologies using leading industry-standard tools.
• Write timing constraints, run STA, and drive timing closure and pipelining at different levels.
• Handle timing closure for multi-clock domain designs and support MCMM synthesis and optimization.
• Implement low-power design flows using UPF and apply power optimization techniques such as clock gating.
• Work with design, DFT, and PD teams to deliver netlists and validate timing constraints.
• Handle ECOs, run formal verification, and maintain a high-quality verification matrix.

What you'll need

• 3+ years (bachelor’s) OR 2+ years (master’s) OR 1+ year (PhD) of ASIC design/verification/validation/integration-related work experience.
• 5 to 8 years of hands-on experience in Synthesis and LEC.
• Strong physical synthesis knowledge and synthesis methodologies with timing constraint writing and STA.
• Experience with timing closure for multi-clock domain designs.
• Familiarity with MCMM synthesis and optimization and low-power implementation using UPF.
• Scripting skills in Perl or Python and TCL.
• Proficiency with Python/Tcl and familiarity with synthesis tools (Fusion Compiler/Genus) and LEC.

Details

• Location: Noida, Uttar Pradesh, India.