Sr. Logic Engineer

Overview

Architect, implement, and deliver complex FPGA-based logic for high-speed protocol analysis and test systems. The role combines hands-on RTL development, transceiver and interface integration, verification, lab debug, and technical leadership across PCIe, CXL, Ethernet, and USB solutions.

What you'll do

• Own FPGA architecture and microarchitecture for protocol capture, packet processing, filtering, triggering, traffic generation, timestamping, and data movement.
• Design, implement, and maintain synthesizable RTL using SystemVerilog, Verilog, or VHDL for high-throughput, low-latency datapaths and control logic.
• Integrate and customize FPGA IP for PCIe, CXL, Ethernet, USB, DDR memory, DMA, and other high-speed interfaces.
• Develop clocking, reset, clock-domain crossing, and data-path schemes across multiple clock domains and transceiver interfaces.
• Optimize designs for timing closure, resource utilization, power, latency, throughput, and design maintainability on large FPGAs.
• Develop FPGA logic for PCIe, CXL, Ethernet, and USB protocol interfaces, including packet framing, flow control, error handling, link monitoring, and protocol-aware processing.
• Work with high-speed serial transceivers, reference clocks, equalization controls, link-training behavior, lane alignment, and multi-lane data paths.
• Partner with protocol, hardware, firmware, and software teams to translate specifications and product requirements into implementable FPGA features.
• Analyze protocol traces and lab measurements to identify interoperability, performance, and corner-case issues.
• Create design specifications, verification plans, assertions, self-checking simulations, constrained-random tests, and reusable testbench components.
• Collaborate with verification engineers using SystemVerilog/UVM and coverage-driven methodologies, and perform block-level and system-level verification.
• Execute synthesis, place-and-route, static timing analysis, CDC/RDC analysis, lint, and design-rule checks, and resolve implementation and timing issues.
• Debug FPGA hardware using embedded logic analyzers such as Vivado ILA or SignalTap, protocol analyzers, oscilloscopes, and other lab equipment.
• Support board bring-up, system integration, regression testing, issue triage, root-cause analysis, and release readiness.
• Provide technical direction for complex features from concept through production release while remaining hands-on in design and debug.
• Lead architecture and RTL reviews, establish coding and verification standards, and drive design quality, reuse, and documentation.
• Mentor engineers in FPGA design, timing closure, high-speed interfaces, protocol behavior, and disciplined problem solving.
• Coordinate with product management, systems engineering, PCB hardware, firmware, software, validation, manufacturing, and customer support teams.
• Communicate technical status, risks, tradeoffs, and recommended actions to engineering and program leadership.

What you'll need

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• Typically 8+ years of relevant digital design experience, with substantial hands-on FPGA development and delivery of production-quality logic.
• Expertise in RTL design with SystemVerilog, Verilog, or VHDL, including synchronous design practices, finite-state machines, pipelining, arbitration, buffering, and error recovery.
• Demonstrated experience with at least two high-speed protocol families among PCIe, CXL, Ethernet, and USB, plus the ability to become effective across the remaining interfaces.
• Strong knowledge of high-speed serial transceivers and FPGA implementation flows on AMD Xilinx UltraScale+/Versal or Intel Stratix/Agilex platforms.
• Proven experience with synthesis, constraints, static timing analysis, timing closure, CDC/RDC, reset architecture, and on-chip debug.
• Experience integrating external memory and high-bandwidth data movement, including DDR4/DDR5, DMA, AXI, Avalon, or comparable on-chip buses.
• Strong debugging and analytical skills across RTL simulation, FPGA implementation, board-level behavior, and protocol-level observations.
• Ability to create clear architecture documents, interface specifications, test plans, and engineering documentation.
• Effective written and verbal communication skills.
• Ability to work from the Pune engineering site in a collaborative product-development environment.

Nice to have

• Deep knowledge of PCIe link and transaction layers, LTSSM behavior, equalization, error handling, and protocol analyzer concepts.
• Experience with CXL.io and familiarity with CXL.cache and CXL.mem concepts, coherency-related flows, or CXL compliance and interoperability challenges.
• Experience with Ethernet MAC/PCS/FEC datapaths, multi-rate designs, high-speed SerDes, or packet processing pipelines.
• Experience with USB 3.x/USB4 protocol logic, Type-C related system considerations, or USB protocol analysis and test.
• Background in protocol analyzers, traffic generators, exercisers, compliance tools, or other test and measurement products.
• Experience with Python, Tcl, C/C++, scripting, continuous integration, automated regression, and source-control workflows such as Git.
• Familiarity with formal verification, FPGA prototyping, hardware emulation, or advanced performance modeling.
• Experience working directly with customers or field teams to resolve complex interoperability and product issues.

Details

• Work location: Pune, Maharashtra, India.
• Work from the Pune engineering site for close collaboration with local and global engineering teams.
• Specific work arrangements, travel expectations, and employment terms will be discussed during the recruiting process.