(India) System IP Design Engineer

Overview

System IP Design Engineer to own microarchitecture and RTL implementation for power management and related subsystems in RISC-V/ARM-based SoCs.

What you'll do

• Own microarchitecture definition and RTL implementation of the Power Management Subsystem.
• Own RTL implementation for Interrupt Controllers.
• Deliver RTL implementation for AXI Interconnect and Cache Controller.
• Collaborate with cross-functional teams (architecture, firmware, software, DV, PD) to define and optimize power management solutions.
• Work with verification teams on assertions, test plans, debug, and coverage.
• Drive verification closure, performance debug, synthesis, timing, and power optimization.

What you'll need

• 5–10 years of experience in ASIC/SOC/IP design.
• Hands-on experience in microarchitecture and RTL development.
• Skilled in Verilog/SystemVerilog.
• Deep understanding of power management concepts including clocking, reset, DVFS, and low-power modes.
• Familiarity with RISC-V or ARM-based SoCs and bus protocols (AXI, AHB, APB, CHI).
• Awareness of functional safety practices (ISO 26262) in hardware design.

Details

• Hybrid work mode based out of Bangalore, India.