Lead PDN/EMIR Engineer

Overview

Lead PDN/EMIR engineering for complex SoCs, owning power delivery network signoff, power integrity closure, methodology development, and cross-functional technical execution through tapeout.

What you'll do

• Own full-chip and subsystem-level PDN signoff.
• Drive power integrity closure across functional, DFT, LBIST, capture, and stress modes.
• Lead package-aware IR/EM analysis and chip-package co-optimization.
• Define power grid architecture, bump planning, power switch strategy, and decap methodology.
• Automate PDN flows and improve runtime, capacity, dashboards, and regressions.
• Drive closure of critical PDN hotspots and present signoff status to stakeholders.
• Mentor engineers and establish PDN signoff governance.

What you'll need

• 8+ years of experience in Physical Design, Power Integrity, or Signoff.
• B.Tech or M.Tech in Electronics, Electrical Engineering, VLSI, or a related field.
• Experience with Vmin, peak EM, dynamic IR, and thermal-aware analysis.
• Programming or scripting experience with TCL, Python, or Shell.
• Experience collaborating with Physical Design, DFT, Package, and Thermal teams.
• Experience supporting silicon bring-up and pre-silicon versus post-silicon correlation.

Details

• Location: Bangalore