Mixed Signal Logic Design Engineer

Overview

Mixed Signal Logic Design Engineer developing high-speed, low-power mixed-signal IPs for next-generation products, owning microarchitecture and RTL delivery.

What you'll do

• Define and implement microarchitecture and RTL designs for mixed-signal and high-speed IP blocks using SystemVerilog.
• Collaborate with architecture and system teams to optimize power, performance, and area.
• Build automation flows and ensure RTL quality using tools such as Lint, CDC, and synthesis QA checks.
• Run power and performance analysis to improve area and power efficiency.
• Review verification plans and resolve RTL issues to ensure feature correctness.
• Support SoC integration by delivering high-quality IP modules.
• Implement automated solutions to streamline coverage closure and timing convergence.

What you'll need

• 4-12 years of experience with a Bachelor's degree OR 3-10 years with a Master's degree.
• Strong expertise in RTL development using SystemVerilog.
• Proficiency in low-power design techniques including UPF, clock gating, and multiple clock domain design.
• Hands-on experience with front-end design tools such as Spyglass, VC Lint, CDC, and synthesis tools.
• Solid understanding of state machine design, simulation, and debugging using VCS and Verdi.
• Scripting proficiency in Perl, Python, or TCL for design automation.

Details

• Location: Bangalore, India.
• Work model: Hybrid (split time between on-site at assigned Intel site and off-site).
• Shift: Shift 1 (India).