Network Processor IP Verification Sr Lead Engineer

Overview

Senior Lead Engineer focused on digital front-end ASIC verification and testing for Qualcomm hardware systems and IP, including RTL/UVM verification and coverage closure.

What you'll do

• Plan, design, and implement digital design verification using SV/UVM/C.
• Build verification environments and testbench components such as BFMs and checkers.
• Perform regression analysis, bug triage, and coverage closure for block/sub-system testing.
• Run performance verification for throughput/latency analysis of modem use cases.
• Conduct power-aware verification on RTL and DC/PD gate-level netlists.
• Coordinate IP integration testing at SoC level and support post-silicon debug.
• Lead junior engineers and drive project planning and tracking.

What you'll need

• 5-8 years of strong experience in digital front-end ASIC design verification.
• Expertise in RTL verification in C/SystemVerilog/UVM of complex designs with multiple clock and power domains.
• Strong coding skills in SystemVerilog and UVM.
• Ability to develop RTL verification assertions for temporal logic testing.
• Scripting and regression automation using Perl/Python and test automation frameworks.
• Understanding of code/functional coverage reports and ability to close coverage by developing new tests.
• Experience with low power verification methodology and clock domain crossing designs.

Details

• Location: Bangalore, India.
• Collaboration: Multi-site teams across US and India and other geos.