NPU / AI Processor Architecture Design-Staff

Overview

Design RTL for DSP processor core logic blocks and support the ASIC frontend design flow through timing, power, verification, and physical design collaboration.

What you'll do

• Develop RTL for multiple DSP core logic blocks.
• Run linting, clock-domain crossing, and synthesis checks.
• Collaborate with physical design on design constraints and timing closure.
• Work with the power team on power optimization.
• Collaborate with verification on test plans, coverage plans, and coverage closure.

What you'll need

• 3–15 years of practical RTL development experience.
• Experience with VHDL and/or Verilog.
• Knowledge of functional and structural RTL design, design partitioning, simulation, and regression.
• Familiarity with ModelSim, VCS, Design Compiler, PrimeTime, linting tools, CDC tools, UPF, code coverage, and SystemVerilog Assertions.
• Bachelor's degree with 4+ years, master's degree with 3+ years, or PhD with 2+ years of relevant experience.
• Experience with RTL design, synthesis, static timing analysis, formal verification, PLDRC, CDC, and low-power techniques.

Nice to have

• Strong processor architecture knowledge.
• Microarchitecture implementation experience.
• Microprocessor integration experience.
• Low-power design experience.

Details

• Location: Bangalore, India.