NSP STA/Timing Engineer

Overview

Hardware engineering role focused on static timing analysis, timing convergence, and methodology development for multi-mode, multi-voltage designs.

What you'll do

• Set up, converge, review, and sign off STA for multi-mode, multi-voltage designs.
• Analyze, validate, and debug timing across multiple PVT conditions.
• Optimize STA flows and correlate Spice results with STA using PrimeTime and/or Tempus.
• Evaluate timing methodologies and tools across designs and technology nodes.
• Develop automation scripts within STA and physical-design tools.
• Drive timing convergence at chip and hard-macro levels.

What you'll need

• Bachelor's degree with 4+ years, master's degree with 3+ years, or PhD with 2+ years of relevant experience.
• Experience in STA/timing analysis, including AOCV/POCV, CTS, and timing constraints.
• Hands-on experience with PrimeTime and Tempus.
• Experience with TCL, Perl, Python, or Awk scripting.
• Familiarity with RTL-to-GDS implementation flows and ICC/ICC2 or Innovus.
• Knowledge of Spice simulation, Hspice/FineSim, Monte Carlo, and silicon-to-Spice correlation.

Nice to have

• 7–14 years of STA/timing experience.
• Knowledge of cross-talk noise, signal integrity, layout parasitic extraction, and feed-through handling.
• Basic knowledge of device physics.

Details

• Location: Bangalore, India.