Physical Design Engineer - Custom Silicon Group

Overview

Physical Design Engineer role in Qualcomm's Custom Silicon Group, working on electronic systems and SoC physical design.

What you'll do

• Plan, design, optimize, verify, and test electronic systems, circuits, and related hardware that launch cutting-edge, world class products.
• Collaborate with cross-functional teams to develop solutions and meet performance requirements.
• Drive Netlist2GDS: floorplan, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.
• Meet demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), including place and route and IP integration.
• Implement low power designs, including Unified Power Format (UPF), multi-voltage domains, and power gating.
• Manage and drive a small team for project execution and PPA targets.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• Bachelor's or Master's degree from a top-tier institute.
• 5 years of experience in physical design from product-based companies.
• Proven experience in managing complex subsystems and small teams.
• Proficiency in complete Netlist2GDS: floorplan, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.
• Hands-on experience in lower technology nodes.
• Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration.
• Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating.
• Familiarity with ASIC design flows and physical design methodologies.
• Strong understanding of circuit design, device physics, and deep sub-micron technology.
• Experience working on multiple technology nodes in advanced processes.
• Proficiency in automation to drive improvements in PPA.

Details

• Location: Bangalore, India.