Senior Engineer ,DPG LPDDR Verification

Overview

Senior Engineer responsible for verification and end-to-end analysis of full-chip gate-level designs for LPDDR and other memory architectures, including low-power and power-management technologies.

What you'll do

• Set verification direction within areas of expertise.
• Simulate, analyze, and debug pre-silicon full-chip designs.
• Develop test cases and stimulus to improve functional coverage.
• Help develop verification methodologies and environments.
• Develop new verification flows with international colleagues.
• Maintain test benches and test vectors, and run coverage regressions.
• Identify verification tasks suitable for AI-based automation and deploy scalable solutions.

What you'll need

• Good communication and teamwork skills.
• Exposure to delayed gate-level simulations.
• Ability to analyze logic schematics and complex CMOS or gate-level circuits.
• Proficiency with SPICE and Verilog simulations.
• Experience in DRAM, SRAM, or related memory fields.
• Experience with Python scripting and setup/hold timing analysis.
• Bachelor's or postgraduate degree in Electronics Engineering or a related engineering field.

Details

• Location: Hyderabad, Telangana, India.