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Senior Physical Design Engineer - Bengaluru, Multiple Vacancies

Graphcore Limited
NewPosted yesterday

LOCATION

Bengaluru · Onsite

EXPERIENCE

3+ Years

SKILLS REQUIRED

Physical DesignTiming AnalysisPhysical VerificationLogic SynthesisPlace and route

Job description

Overview

Contribute to the physical design of Graphcore's next generation of AI superchips, delivering robust, high-performance, power-efficient designs in leading-edge process technologies within the silicon design team in Bengaluru.

What you'll do

  • Use state-of-the-art EDA tools and in-house Graphcore flows to deliver final designs of sign-off quality.
  • Enhance existing flows and in-house tools/APIs to support new features and/or methodologies.
  • Analyse and/or debug complex engineering problems leading to workable solutions.
  • Develop an understanding of emerging technical issues and apply that knowledge to optimise in-house flows and methodologies.
  • Work closely with other Graphcore teams and with 3rd party support engineers/contractors, ensuring good communication between all parties.

What you'll need

  • A degree in Electronic/Electrical Engineering, Computer Science or related subject, with 3+ years of industry experience.
  • Highly motivated, a self-starter and a team player.
  • Excellent problem-solving skills for debugging issues and finding root causes.
  • Ability to program/script (required to solve design issues, typically in Tcl and Python).
  • Experience in 7nm or smaller technologies.
  • A good breadth of experience with physical design flows including floorplanning/budgeting, synthesis, place and route, clock CTS, logical equivalence, timing analysis, and physical verification (DRC/LVS/ERC).

Nice to have

  • In-depth expertise in one or more aspects of physical design flows.
  • Structuring of builds to maximise PPA.
  • Silicon transistor knowledge including std cell libraries and/or memories.
  • 2D and 3D design (CoWoS, UCIe etc.).
  • High speed, high power and/or full reticle chip design.
  • Ethernet, PCIe, LPDDR, HBM interfaces.
  • Power integrity and optimisation.
  • 2nm or 3nm technologies.
  • Chip finishing (pad rings, chip level LVS/DRC/ERC).
  • Design for test.
  • Team management.
  • Project planning.

Details

  • Location: Bengaluru, India (new AI Engineering Campus).
  • Multiple roles across different levels.

Read the full description and apply on the company’s own careers page.

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Senior Physical Design Engineer - Bengaluru, Multiple Vacancies