Senior Staff VLSI Design Engineer (SystemC, Functional Modeling, C++ , Verification)

Overview

Senior Staff VLSI Design Engineer to develop and verify functional models using SystemC/C++ and create and debug test environments.

What you'll do

• Code C++ and SystemC models and build test creation workflows.
• Debug issues in a firmware environment.
• Validate the developed model using SystemC/SV/UVM testbench.
• Debug failures and perform root-cause analysis by interacting with other teams/groups.
• Mentor junior engineers.

What you'll need

• 13+ years of relevant experience.
• Hands-on functional modeling and verification experience with C++ and SystemC model development and test creation.
• Prior experience with C-based tests/testbench development.
• Electronics and communication/embedded systems background for bachelor’s/master’s degree.
• Problem-solving skills.
• Team leading and mentoring skills.

Nice to have

• Python coding.
• Knowledge of NAND concepts.
• Knowledge of memory and digital design concepts (SRAM/DRAM/ROM/Flash).
• Circuits/logic knowledge.
• Experience/knowledge of Verilog/SystemVerilog/UVM.
• Tool expertise with VisualStudio, Git, and Bitbucket.

Details

• Location: Bengaluru, KA, India.