Staff ASIC Digital Engineer (SOC Verification, UVM) with 8 to 12 years of experience

Overview

Staff ASIC Digital Engineer (SoC Verification, UVM) to develop verification test plans, tests, and test benches for complex SoC ASICs.

What you'll do

• Drive verification strategy and create test plans for SoC verification.
• Develop test benches for SoC and collaborate with architects/designers and verification teams.
• Develop C-based tests targeting SoC verification.
• Define and meet functional coverage goals.
• Run and debug gate-level simulations.
• Understand and generate functional patterns for ATE.

What you'll need

• BE or MS in Electrical Engineering or Computer Engineering.
• 9-13 years of experience (experience range stated in the requirements).
• Deep understanding of C, SystemVerilog UVM, and coverage-driven verification methodology.
• History of building and improving UVM-based verification methodology.
• Proficiency with C, Verilog, SystemVerilog, and verification.
• Experience implementing advanced test benches, verification models, and scoreboards/checkers.
• Knowledge of bus protocols including APB, AHB, AXI, and bus interconnects.

Details

• Location: Bengaluru, KA, India.