Staff Engineer, SoC Design Verification

Overview

Staff/SoC design verification engineer focused on pre-silicon verification of PCIe logic in advanced AI SoCs.

What you'll do

• Develop and own verification environments for PCIe logic across AI chiplets and SoCs.
• Write, refine, and execute test scenarios for link training, enumeration, and power management.
• Test error handling and data movement features for PCIe logic.
• Analyze coverage gaps, debug failures, and collaborate with architecture, RTL, and system teams.
• Automate PCIe protocol testing and interoperability validation flows.
• Integrate AI productivity tools for verification workflows.

What you'll need

• Deep curiosity about PCIe architecture and link behavior.
• Expertise in UVM and verification of PCIe controller, PHY-facing logic, LTSSM, and protocol flows.
• Comfort with PCIe Gen4/Gen5 features and compliance concepts.
• Experience with advanced verification automation.
• Ideally familiar with tools similar to CocoTB.

Details

• Work mode: Hybrid; based out of Boston, MA; Toronto; Ottawa; or Santa Clara, CA.