Staff Engineer, VLSI Design Engineering

Overview

Staff Engineer focused on VLSI design verification, leading test planning, verification strategies, and verification infrastructure for complex IP and SoC designs.

What you'll do

• Lead development and execution of comprehensive test plans and verification strategies.
• Design and implement UVM-based verification environments for IP blocks and SoC designs.
• Develop reusable verification components such as bus functional models, monitors, checkers, and scoreboards.
• Drive functional coverage planning, development, debug, and verification closure.
• Develop and maintain SystemVerilog Assertions (SVA) including coding, porting, and maintenance.
• Collaborate with RTL designers and post-silicon validation teams to integrate verification seamlessly.
• Create verification automation tools and scripts to improve productivity.

What you'll need

• Have 8 to 11 years of relevant experience.
• Proficiency in C, Verilog, SystemVerilog, and UVM.
• Hands-on experience with Xcellium, Verdi, and JasperGold formal verification tools.
• Experience across the verification lifecycle: planning, testbench and test case development, regression management, coverage analysis, debugging, and sign-off.
• B.E/B.Tech/M.Tech in ECE, VLSI, or Electrical Engineering.
• Ability to lead technical projects and manage stakeholder relationships.
• Excellent written and verbal communication skills.

Nice to have

• Experience with NAND flash memory protocols and memory design verification.
• Experience with formal verification methodologies and assertion-based verification.
• Track record of mentoring junior engineers and contributing to process improvements.
• Experience/exposure with Xcelium simulator, Verdi Debugger, JasperGold Formal, and Vmanager Regression manager.

Details

• Location: Bengaluru, KA, India.