Tech Lead, Formal Verification

Overview

Tech Lead responsible for leading formal verification for complex IP and SoC designs.

What you'll do

• Develop formal verification plans from architecture and design specifications.
• Develop and execute formal verification environments, assertions, properties, and checkers.
• Drive proof convergence using abstraction and complexity reduction techniques.
• Collaborate with Architecture, RTL Design, and Design Verification teams on design intent and verification requirements.
• Evaluate, deploy, and scale formal verification methodologies, flows, and tools across projects.
• Lead technical mentorship, bug triage, and root-cause analysis for verification issues.
• Estimate verification effort, track progress, identify risks, and support mitigation planning.

What you'll need

• 5–10 years of experience in semiconductor verification with significant formal verification experience.
• Expert knowledge of SystemVerilog and SVA plus verification planning & closure and ABV techniques.
• Hands-on experience with formal verification tools such as JG or VCF.
• Experience verifying complex protocols, control logic, and SoC or subsystem-level designs.
• Strong scripting skills in Python, Perl, Tcl, or Shell.
• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• Experience leading technical efforts or mentoring team members.

Details

• Role requires close collaboration with Architecture, RTL Design, and Design Verification teams.