Trainee Engineer

Overview

Trainee Engineer role in Digital Design Verification within Infineon's Silicon Engineering team, focused on functional verification of Graphics and Security IP.

What you'll do

• Assist in developing, maintaining, and enhancing block-level and chip-level simulation testbenches.
• Write scalable verification components, including drivers, monitors, predictors, and scoreboards using SystemVerilog (SV) and UVM.
• Collaborate with senior engineers to bring up emulation testbenches for hardware-accelerated verification and pre-silicon validation.
• Learn the architecture of Graphics IPs (pipelines, shaders, or memory controllers) and map out comprehensive verification plans.
• Run regressions, debug hardware failures using waveform viewers, and write functional coverage covergroups to achieve 100% verification closure.

What you'll need

• Bachelor's or master's degree in Electronics Engineering, Computer Engineering, Computer Science, or a related field.
• Graduation date within the last 12 months.
• Strong foundational knowledge of SystemVerilog (SV).
• Exposure to UVM (Universal Verification Methodology) through university coursework, lab projects, or internships.
• Solid understanding of digital logic design, computer architecture, and FIFO/arbitration mechanisms.
• Basic proficiency in scripting languages like Python, Perl, or Bash for automation.

Nice to have

• Prior internship experience in ASIC/FPGA design or verification.
• Direct project experience involving Graphics IP, GPU architectures, or high-throughput data pipelines.
• Familiarity with hardware emulation platforms (e.g., Palladium, Zebu, Veloce) or FPGA prototyping.
• Experience with EDA tools from Synopsys, Cadence, or Siemens (e.g., VCS, Questa, Xcelium).

Details

• Location: Bangalore.