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Senior Principal Design Verification Engineer Jobs
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Senior Principal Engineer, SoC Design Verification
New
GlobalFoundries Inc.
Hyderabad · Onsite
8+ Years
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Systemverilog
UVM
Functional coverage
+1
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Posted today
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DDR Design Verification Lead Engineer
New
Qualcomm
Hyderabad · Onsite
11+ Years
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UVM
Systemverilog
Debugging
+1
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Posted today
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Silicon Design Verification Engineer
New
Intel
Bangalore · Hybrid
3+ Years
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Verification Planning
Verilog
Debugging
+1
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Posted yesterday
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ASIC Design Verification Engineer || Verilog, UVM, Testbench | Simulation || Exp 7+ years
Cisco
Bangalore · Onsite
7+ Years
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Verilog
Verification Planning
Coverage Modeling
+1
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Posted this week
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Design Verification - Senior Staff Engineer/Mgr
New
Qualcomm
Hyderabad · Onsite
11+ Years
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Coverage closure
Assertions
Debugging
Verilog
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Posted today
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SoC Design Verification Engineer
Intel
Bangalore · Hybrid
6+ Years
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UVM
Debugging
Verification Planning
+1
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Posted this week
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Video IP Design Verification Engineer
Qualcomm
Bangalore · Onsite
3 - 13 Years
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Systemverilog
UVM
coverage driven verification
+1
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Posted this week
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RTL Design Verification (NOC)- Engineer
Qualcomm
Bangalore · Onsite
1+ Years
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Digital Logic
Verilog
Debugging
Hardware Design
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Posted this week
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ASIC Design Verification Engineer
Hewlett Packard Enterprise
Bengaluru · Onsite
5+ Years
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Systemverilog
UVM
Verification Planning
+1
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Posted this week
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Digital Design Verification Engineer
Altera
Iași · Remote
0 - 5 Years
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Systemverilog
CI/CD
System Verification
+1
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Posted 3 weeks ago
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