What is the default mode for a port variable?

Which of the following in structural modeling is similar to the entity declaration?

Refer to the VHDL code given below, how many input-output pins are there in MUX entity? ENTITY mux IS Port ( a,b : IN STD_LOGIC; Y : OUT STD_LOGIC); END mux;

What is the purpose of using Generics in VHDL?

Which of the following is the correct syntax for declaring a SUBTYPE?

How to correctly assign the value of 2x+10 to y in the following VHDL code?

TYPE long IS INTEGER RANGE -1000 TO 1000;
TYPE short IS INTEGER RANGE -10 TO 10;
SIGNAL x : short;
SIGNAL y : long;

A component has 3 ports - two inputs (a and b) and one output (y). Which of the following statements is correct for the positional mapping of the component?

What will be the value of y after the execution of the following VHDL code?

Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
...
SIGNAL m : UNSIGNED (3 DOWNTO 0);
SIGNAL n : UNSIGNED (3 DOWNTO 0);
SIGNAL y : STD_LOGIC_VECTOR (7 DOWNTO 0);
y <= CONV_STD_LOGIC_VECTOR ((m + n), 8);

How to declare a 2 input OR gate in the structural modeling?

a)

  COMPONENT or IS
    PORT ( a, b : IN BIT;
            x, y : OUT BIT);
   END COMPONENT;

b)

   COMPONENT or IS
    PORT ( a, b : IN BIT;
               y : OUT BIT);
   END COMPONENT;

c)

  COMPONENT or_gate IS
    PORT ( a, b : IN BIT;
            x,  y : OUT BIT);
   END COMPONENT;

d)

  COMPONENT or_gate IS
    PORT ( a, b : IN BIT;
              y : OUT BIT);
   END COMPONENT;