CPU STA/Timing Engineer (Lead/Staff/Sr Staff)

Overview

CPU Physical Design Timing (STA) Engineer to support high-performance CPU core and uncore designs through timing analysis and closure.

What you'll do

• Define, implement, and validate timing constraints with microarchitecture, RTL, and DFT teams.
• Perform STA across block, cluster, and SoC/top-level hierarchies across modes, corners, and scenarios.
• Analyze timing on frequency-critical paths and collaborate for logic and micro-architectural fixes.
• Provide actionable timing feedback to physical design engineers to achieve CPU frequency and timing closure.
• Develop and enhance CPU-specific timing flows and infrastructure with CAD/methodology teams.
• Generate and review timing ECOs to close setup, hold, noise, and cross-talk violations.

What you'll need

• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• 2+ years of Hardware Engineering or related work experience (or 1+ year with a Master’s; or PhD).
• Hand-on experience with STA/timing closure (for preferred qualifications).
• Ability to work with CPU architects, RTL designers, PD, and CAD teams (communication skills stated as preferred).

Nice to have

• MS in Electrical Engineering with 3+ years of hands-on STA and timing closure experience.
• Strong experience with STA and timing closure for high-performance CPU/processor-class SoCs.
• Expertise in multi-clock, multi-domain CPU designs with aggressive frequency targets.
• Experience with deep sub-micron technology nodes and advanced process technologies.

Details

• Location: Bangalore, India.