Lead I/O Design Engineer

Overview

Lead I/O Circuit Design Engineer to design and validate high-performance I/O circuits for advanced semiconductor SoCs, covering custom interfaces, ESD, and signal integrity through silicon bring-up.

What you'll do

• Design and develop custom IO circuits for GPIO, LVDS, LVCMOS, SSTL, HSTL, DDR interfaces, and high-speed SerDes support.
• Perform transistor-level design and simulation using advanced CMOS technology nodes.
• Develop and optimize ESD protection, level shifters, input buffers, output drivers, and on-chip termination circuits.
• Run pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.
• Conduct signal integrity analysis including IBIS model generation and package-aware simulations for crosstalk and reflections.
• Support silicon bring-up with characterization, debugging, and production ramp activities.

What you'll need

• 5-8 years of experience in Analog/Mixed-Signal or IO Circuit Design.
• Hands-on experience with Cadence Virtuoso.
• Expertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.
• Strong understanding of CMOS device physics, analog circuit design fundamentals, IO architectures/standards, and ESD design methodologies.
• Knowledge of LVS, DRC, EMIR, and reliability checks.
• Familiarity with process corners, Monte Carlo analysis, and yield optimization techniques.
• Bachelor's or Master's degree in a relevant engineering field.

Details

• Location: Bangalore.