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Physical Design Engineer

Qualcomm

Posted this week

LOCATION

Noida · Onsite

EXPERIENCE

8+ Years

SALARY

Negotiable

SKILLS REQUIRED

Unix/LinuxLEC and CLP SignoffClock Tree SynthesisPlacement OptimizationLow Power Verification

Job description

Overview

Physical Design Engineer role focused on planning, implementing, and signing off PNR flows for Qualcomm SoCs on latest technology nodes.

What you'll do

Own PNR implementation including floorplanning, placement, CTS, and post-route.
Run/execute PNR implementation workflows on latest nodes.
Apply signoff knowledge across STA, power analysis, FV, and low-power verification/PV.

What you'll need

Bachelor’s degree in a relevant field with 8+ years of hardware engineering experience, or Master’s with 7+ years, or PhD with 6+ years.
Hands-on experience with floorplanning, PNR, and STA flows.
Knowledge of placement and clock tree synthesis (CTS) including optimization.
Signoff domain understanding including LEC/CLP/PDN knowledge.
Unix/Linux knowledge with Perl/TCL fundamentals for scripting.

Details

Location: Noida, Uttar Pradesh, India.

Read the full description and apply on the company’s own careers page.

Hiring on Abekus is free for applicants

We never charge a fee, and employers are prohibited from doing so. If a recruiter asks for payment, please report them right away.

Physical Design Engineer

Qualcomm

Posted this week

LOCATION

Noida · Onsite

EXPERIENCE

8+ Years

SALARY

Negotiable

SKILLS REQUIRED

Unix/LinuxLEC and CLP SignoffClock Tree SynthesisPlacement OptimizationLow Power Verification

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Job description

Overview

Physical Design Engineer role focused on planning, implementing, and signing off PNR flows for Qualcomm SoCs on latest technology nodes.

What you'll do

Own PNR implementation including floorplanning, placement, CTS, and post-route.
Run/execute PNR implementation workflows on latest nodes.
Apply signoff knowledge across STA, power analysis, FV, and low-power verification/PV.

What you'll need

Bachelor’s degree in a relevant field with 8+ years of hardware engineering experience, or Master’s with 7+ years, or PhD with 6+ years.
Hands-on experience with floorplanning, PNR, and STA flows.
Knowledge of placement and clock tree synthesis (CTS) including optimization.
Signoff domain understanding including LEC/CLP/PDN knowledge.
Unix/Linux knowledge with Perl/TCL fundamentals for scripting.

Details

Location: Noida, Uttar Pradesh, India.

Read the full description and apply on the company’s own careers page.

Hiring on Abekus is free for applicants

We never charge a fee, and employers are prohibited from doing so. If a recruiter asks for payment, please report them right away.

Physical Design Engineer

Physical Design Engineer

Job description

Physical Design Engineer

Get certified in what this role needs

Job description

Get certified in what this role needs

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