Physical Design Senior Staff Engineer

Overview

Physical design (PNR) senior staff engineer role on the ASIC engineering team, implementing and signing off Qualcomm SoCs on latest technology nodes.

What you'll do

• Take complete ownership of PNR implementation (floorplanning, placement, CTS, post-route) on latest nodes.
• Carry out signoff work, including STA, power analysis, FV, low power verification and PV.
• Collaborate with cross-functional groups to determine the product execution path.

What you'll need

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• 10+ years of hardware engineering experience or related work experience.
• 10+ years of experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm).
• Good hands-on experience with floorplanning, PNR and STA flows.
• Good knowledge of placement and clock tree synthesis (CTS), optimization, etc.
• Good understanding of signoff domains, including LEC/CLP/PDN knowledge.
• Good knowledge of Unix/Linux and Perl/TCL fundamentals and scripting.
• Good analytical and problem-solving skills, and a quick learner.

Details

• Location: Noida, Uttar Pradesh, India.
• Employment type and work mode not stated.