Principal Engineer, Digital Design

Overview

Principal IC Design Engineer (RTL Design) for MCU SoCs, leading RTL design and subsystem delivery with responsibility for design quality and end-to-end integration.

What you'll do

• Lead RTL design and development of complex IPs and subsystems within MCU SoCs with PPA compliance.
• Drive micro-architecture definition and high-level digital design for assigned blocks.
• Support SoC integration by providing subsystem views and documentation to Back-end and Design Verification teams.
• Own design quality checks including lint, CDC, and RDC, and support functional verification.
• Collaborate with system architects, verification engineers, physical design teams, and software teams to define specifications.
• Mentor junior engineers and evolve RTL design methodologies, coding guidelines, and design processes.

What you'll need

• Minimum 15 years of hands-on experience in digital IC/ASIC design with a track record of delivering high-quality silicon.
• Strong expertise in RTL design using Verilog/VHDL.
• Strong understanding of digital design principles, timing analysis, clocking, resets, and verification methodologies.
• Experience using industry-standard EDA tools for synthesis, simulation, and static timing analysis.
• Strong problem-solving skills with ability to own blocks end-to-end.
• Bachelor’s degree in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, or related field.

Details

• Location: Bengaluru, KA, India.